Задана архитектура компонента на языке VHDL. Какого компонента?

architecture Behavioral of comp is
component DFF -- D триггер
port ( D,C,R : in std_logic;
Q : out std_logic);
end component;
signal T: std_logic_vector(0 to 11);
begin
T(0)<=L;
LFSR<=T(11);
ST0: DFF port map(D=>T(0),C=>Clock,R=>reset,Q=>T(1));
JK1: for i in 1 to 10 generate
begin
ST2: DFF port map(D=>T(i),C=>Clock,R=>reset,Q=>T(i+1));
end generate;
end Behavioral;